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Raspberry Pi /RP2350 /CLOCKS /ENABLED1

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Interpret as ENABLED1

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https://regviz.com/r/Raspberry Pi/RP2350/CLOCKS/ENABLED1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_PERI_SPI0)CLK_PERI_SPI0 0 (CLK_SYS_SPI0)CLK_SYS_SPI0 0 (CLK_PERI_SPI1)CLK_PERI_SPI1 0 (CLK_SYS_SPI1)CLK_SYS_SPI1 0 (CLK_SYS_SRAM0)CLK_SYS_SRAM0 0 (CLK_SYS_SRAM1)CLK_SYS_SRAM1 0 (CLK_SYS_SRAM2)CLK_SYS_SRAM2 0 (CLK_SYS_SRAM3)CLK_SYS_SRAM3 0 (CLK_SYS_SRAM4)CLK_SYS_SRAM4 0 (CLK_SYS_SRAM5)CLK_SYS_SRAM5 0 (CLK_SYS_SRAM6)CLK_SYS_SRAM6 0 (CLK_SYS_SRAM7)CLK_SYS_SRAM7 0 (CLK_SYS_SRAM8)CLK_SYS_SRAM8 0 (CLK_SYS_SRAM9)CLK_SYS_SRAM9 0 (CLK_SYS_SYSCFG)CLK_SYS_SYSCFG 0 (CLK_SYS_SYSINFO)CLK_SYS_SYSINFO 0 (CLK_SYS_TBMAN)CLK_SYS_TBMAN 0 (CLK_REF_TICKS)CLK_REF_TICKS 0 (CLK_SYS_TICKS)CLK_SYS_TICKS 0 (CLK_SYS_TIMER0)CLK_SYS_TIMER0 0 (CLK_SYS_TIMER1)CLK_SYS_TIMER1 0 (CLK_SYS_TRNG)CLK_SYS_TRNG 0 (CLK_PERI_UART0)CLK_PERI_UART0 0 (CLK_SYS_UART0)CLK_SYS_UART0 0 (CLK_PERI_UART1)CLK_PERI_UART1 0 (CLK_SYS_UART1)CLK_SYS_UART1 0 (CLK_SYS_USBCTRL)CLK_SYS_USBCTRL 0 (CLK_USB)CLK_USB 0 (CLK_SYS_WATCHDOG)CLK_SYS_WATCHDOG 0 (CLK_SYS_XIP)CLK_SYS_XIP 0 (CLK_SYS_XOSC)CLK_SYS_XOSC

Description

indicates the state of the clock enable

Fields

CLK_PERI_SPI0
CLK_SYS_SPI0
CLK_PERI_SPI1
CLK_SYS_SPI1
CLK_SYS_SRAM0
CLK_SYS_SRAM1
CLK_SYS_SRAM2
CLK_SYS_SRAM3
CLK_SYS_SRAM4
CLK_SYS_SRAM5
CLK_SYS_SRAM6
CLK_SYS_SRAM7
CLK_SYS_SRAM8
CLK_SYS_SRAM9
CLK_SYS_SYSCFG
CLK_SYS_SYSINFO
CLK_SYS_TBMAN
CLK_REF_TICKS
CLK_SYS_TICKS
CLK_SYS_TIMER0
CLK_SYS_TIMER1
CLK_SYS_TRNG
CLK_PERI_UART0
CLK_SYS_UART0
CLK_PERI_UART1
CLK_SYS_UART1
CLK_SYS_USBCTRL
CLK_USB
CLK_SYS_WATCHDOG
CLK_SYS_XIP
CLK_SYS_XOSC

Links

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Register License

Copyright © 2024 Raspberry Pi Ltd.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data